Institut für Rechnerarchitektur
und Parallelrechner
Vorlesungen für das aktuelle Semester WS15
Multicore System Architecture
Dozent: Prof. Dr. Wolfgang J. Paul
Assistent: Dr. Geng Chen
Ort: E1.3, HS003
Zeit: Tuesday,14:00-16:00 and Friday,10:00-12:00
Teilgebiet: Advanced course
Inhalt: This is the counter part of the lecture ‚System Architecture‘ for multicore systems. It builds on the material of lectures ’System Architecture' and on the lecture ‚Computer Architecture 1‘. Although we will summarize the material that we use, a student of this class should have heard at least one of these lectures or reserve substantial amounts of time for reading up on this material.
The class has three portions:
  • Hardware: the pipelined multi core processor from the computer architecture class is augmented with store buffers and operating system support: interrupts, multi level address translation, nested page tables, inter processor interrupts.
  • Structured Parallel C: A theory of store buffer reduction and order reduction is presented. This permits to define the semantics of structured parallel C (which uses a sequentially consistent memory model without store buffers) and to extend the C-compiler from the ‚System Achitecture‘ class for the translation of multiple C-threads operating on a shared global memory and heap.
  • Hypervisor: In a nutshell a hypervisor is a kernel, whose guests are operating systems together with their user processes. Thus, in contrast to ordinary kernels the guests can run in translated mode. This is supported by memory management unit (MMUs) with nested page tables. Building on the kernel from the ‚System Architecture‘ lecture, we will outline the construction of a hypervisor for a multicore machine and its correctness proof.
Scheinvergabe: Oral exam.
Prerequisites: 50% of all exercise points.
In addition, each student must present a solution of an exercise at least two times during tutorials.

Praktika für das Semester SS15
Hardware Design Praktikum (HaDePrak)
Assistent: M. Sc. Petro Lutsyk
Ort: Lehrstuhl Prof. Paul, Geb. E 1.3
Zeit: 7. September - 25. September 2015. Weekdays, from 9-00 to 13-00
Teilgebiet: Grundstudium
Inhalt: In diesem Blockkurs lernen die Teilnehmer den Gebrauch des ISE-Designsystems, mit dem man digitale Hardwaredesigns auf field programmable gate arrays (FPGA’s) implementieren kann. Als größeres Beispiel wird der sequentielle MIPS-Prozessor aus den Vorlesungen ‚Systemarchitektur‘ bzw. ‚Computer Architecture 1‘ implementiert und zum Laufen gebracht. Die Veranstaltung wird sowohl auf Deutsch als auch auf Englisch angeboten.
Kontakt (Deutsch): Felix Schmidt
Contents: In this block course the participants learn to use the ISE toolchain, which allows to implemented digital hardware designs on Xilinx field programmable gate arrays (FPGAs). As a major example the sequential MIPS processor from the lectures ‚System Architecture‘ resp. ‚Computer Architecture 1‘ is realised and debugged. The class is offered both in English and in German.
Contact (English): Petro Lutsyk
Scheinvergabe: Teilnahme an den Übungen, bestandene Abschlussklausur

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