GeNoC: A Generic Network On Chip

The design of complex systems on a chip (SoC) relies on the integration of pre-existing modules. In this framework, the overall behavior of SoC's highly depends on the interconnect structure. Its design and the verification of the communication architecture become crucial. In this project, we aim at defining a generic network model and a refinement methodology to formally verify networks on a chip (NoC's).

Julien Schmaltz
Last modified: Thu Jul 6 14:52:10 CEST 2006